Barrel-as-trace estimate · legacy IPC-2221 relationship

PCB Via Current Calculator

Estimate a plated via or an equal-sharing array with an unrolled-barrel trace analogy. Solve current, via count or temperature rise within the tool’s stated limits, then verify the real board construction.

Maintained by Giorgi Gaprindashvili Published June 26, 2026 Updated September 18, 2026 Editorial check September 2026

Barrel-as-trace estimate with equal current sharing. This is not a validated via-current rating and no copper-plane bonus is applied.

Solve for

Via type ?

Finished hole diameter ?

Plating thickness ?

Via length (board thickness) ?

Heat sinking ?

Allowed temperature rise ?

°C

Number of vias ?

Method based on Legacy trace-current analogy; not a normative via-rating method · editorial check September 2026 · revision 1.1

Why a via behaves like a short trace

A plated via carries current in the copper barrel on the hole wall. Unrolled, the barrel is a short trace whose area is roughly the hole circumference times the plating thickness.

Single through-hole via, 25 um plating, isolated, 10 C rise

Calculated from the same unrolled-barrel heuristic at a 10 °C rise. The alternate legacy coefficient halves the current estimate; no plane bonus or guaranteed thermal accuracy is implied.
Finished hole	Barrel area	Current (per via)
0.2 mm (8 mil)	27 mil²	1.5 A
0.3 mm (12 mil)	40 mil²	1.9 A
0.4 mm (16 mil)	52 mil²	2.3 A
0.5 mm (20 mil)	64 mil²	2.7 A
0.6 mm (24 mil)	76 mil²	3.1 A
0.8 mm (31 mil)	100 mil²	3.7 A

A via is a rolled-up trace

The current does not flow through the empty hole - it flows through the thin copper plated onto the hole wall, a hollow cylinder called the barrel. Unroll that cylinder and you have a short, narrow trace whose width is the hole circumference and whose thickness is the plating. So the via obeys the same IPC-2221 relation as any conductor: I = k x dT^0.44 x A^0.725, with A the barrel's copper cross-section.

The exact barrel area is the annulus pi x t x (d + t), where d is the finished hole diameter and t the plating thickness; for thin plating this is close to the simpler pi x d x t. Because area enters with a 0.725 exponent, doubling the plating does not double the current - it adds roughly 65%. That is why drill size and plating thickness, not pad diameter, drive the result.

Through-hole, blind and buried

The legacy relationship uses different fitted constants for external and internal traces. That difference is not a physical rule that buried copper always runs hotter. Heat flows through the board and connected copper as well as into the surrounding air; the actual stackup determines the temperature. Applying either constant to a via remains a trace analogy, not a via-specific certification method.

Why power nets use via arrays

The arithmetic assumes equal current sharing among identical parallel vias. Actual sharing and temperature depend on connections, geometry, tolerances and neighboring heat sources. The tool applies no generic copper-plane multiplier.

Worked examples

Real sizing calls, and the number that decides each one.

Scenario	Result	Why
0.3 mm via, 25 µm (1 mil) plating, 20 °C rise	2.6 A per via	Barrel copper area A = π·t·(d+t) is about 40 mil²; the IPC-2221 method gives roughly 2.6 A at a 20 °C rise on an external via.
0.2 mm via, 25 µm plating, 10 °C rise	1.5 A per via	A smaller barrel (about 28 mil²) and a tighter temperature budget bring the per-via current down to around 1.5 A.
Carrying 5 A through 0.3 mm vias, 20 °C rise	2 vias	At about 2.6 A each, two vias in parallel carry the 5 A with margin. Size a via array the way you size a trace.

How this relates to other standards

Standard / tool	Relationship	What it means
IPC-2221C §6.2	Method from	The conductor current-vs-area-vs-temperature relation, applied here to the via barrel instead of a trace.
IPC-2152	Refined by	A 2009 current-capacity reference with broader thermal data than the legacy trace equation; IPC currently lists the document as “No Longer Maintained”. It does not turn this via analogy into a validated via rating.
PCB trace width	Same standard as	The trace either side of the via is sized by the same IPC-2221 method - size them together so the via is not the bottleneck.

A barrel-as-trace heuristic with equal current sharing, not a validated via-current rating. No generic plane bonus is applied. Verify plating, connections and actual thermal behavior before using the result for a production board.

Where engineers use this

Layer-to-layer power delivery

Stitching a power rail from a top-side connector down to inner planes, where one via is rarely enough and an array shares the current.

Point-of-load regulators

Sizing the via array on a buck converter output so the barrels carry the rail current without becoming the hot spot.

Thermal vias under power parts

Estimating how an array of plated vias both carries current and conducts heat into an inner plane below a hot component.

Frequently asked questions

Does the hole diameter or the plating set the current?

Both, through the barrel cross-section. A bigger hole gives more circumference and thicker plating gives more wall, and the product (about pi x drill x plating) is the copper area that carries current. The empty hole carries nothing, which is why a large unplated-looking via can still be limited by thin plating.

Should I use the inner or outer IPC-2221 constant for a via?

The tool retains 0.048 and 0.024 as selectable legacy trace coefficients for comparison. Neither coefficient becomes a validated via rating merely because the via is through-hole or blind/buried.

How many vias do I need for a power rail?

The Vias needed mode rounds up the count implied by the heuristic and assumes equal current sharing. Check actual plating, connections and thermal behavior before selecting the production array.

Is IPC-2221 accurate for vias?

It is an analogy to a trace equation. Numerical verification of the arithmetic does not validate via heating or establish that the estimate is conservative. Use it for a preliminary discussion with the fabricator.

Does this cover high-frequency or current crowding?

No. The model is steady-state DC. It does not include skin effect, current crowding at the via transition, or via inductance, all of which matter at high frequency or fast edges. For signal integrity, use an impedance and return-path analysis instead.

Does via-in-pad or filled/capped via change the rating?

Filling, capping and via-in-pad construction change the thermal path. This tool does not model those changes. Obtain construction-specific guidance and minimum plating data from the fabricator.

Related standards

IPC-2221 (generic PCB design)

Guides

IPC-2221 vs IPC-2152Why the two standards disagree, and which to trust.

Sources: IPC-2221C, general PCB design reference; the calculator uses a legacy trace analogy · IPC-2152 (2009), published current-capacity reference; IPC revision table lists it as No Longer Maintained. Verify against the current edition.