IPC-2221 · §6.2

PCB Via Current Calculator

Size a plated through-hole via, or a via array, for the current it must carry between layers - using the same IPC-2221 method as a trace, applied to the copper barrel. Solve for the current an array can carry, the number of vias a current needs, or the temperature rise at a given current.

Solve for

Via type ?

Finished hole diameter ?

Plating thickness ?

Via length (board thickness) ?

Heat sinking ?

Allowed temperature rise ?

°C

Number of vias ?

Method based on IPC-2221C (2023) · reviewed June 2026 · method rev 1.0

Why a via behaves like a short trace

A plated via carries current in the copper barrel on the hole wall. Unrolled, the barrel is a short trace whose area is roughly the hole circumference times the plating thickness.

Single through-hole via, 25 um plating, isolated, 10 C rise

First-pass values at a 10 C rise. Blind/buried vias carry roughly 40% of these; a 20 C rise raises them about 35%; a plane connection adds about 20%.
Finished hole	Barrel area	Current (per via)
0.2 mm (8 mil)	27 mil²	1.5 A
0.3 mm (12 mil)	40 mil²	1.9 A
0.4 mm (16 mil)	52 mil²	2.3 A
0.5 mm (20 mil)	64 mil²	2.7 A
0.6 mm (24 mil)	76 mil²	3.1 A
0.8 mm (31 mil)	100 mil²	3.7 A

A via is a rolled-up trace

The current does not flow through the empty hole - it flows through the thin copper plated onto the hole wall, a hollow cylinder called the barrel. Unroll that cylinder and you have a short, narrow trace whose width is the hole circumference and whose thickness is the plating. So the via obeys the same IPC-2221 relation as any conductor: I = k x dT^0.44 x A^0.725, with A the barrel's copper cross-section.

The exact barrel area is the annulus pi x t x (d + t), where d is the finished hole diameter and t the plating thickness; for thin plating this is close to the simpler pi x d x t. Because area enters with a 0.725 exponent, doubling the plating does not double the current - it adds roughly 65%. That is why drill size and plating thickness, not pad diameter, drive the result.

Through-hole, blind and buried

A through-hole via connects to the outer layers and gets a little convection, so the common convention - and the one this tool uses - applies the IPC-2221 outer-layer constant (k = 0.048). Blind and buried vias are sealed between inner layers with no air path, so they use the inner-layer constant (k = 0.024), which roughly halves the rating for the same geometry. Some engineers treat every via as inner-layer for conservatism on critical power paths; if in doubt, take the lower number or add margin.

Why power nets use via arrays

One small via is a poor conductor and a worse heat path, so power that changes layers is carried by several vias in parallel. The array capacity is close to the per-via current times the count, but vias packed tightly into a farm heat each other, so derate a dense array and keep a margin. A via dropped onto a copper plane sheds heat into it and carries more - about 1.2x - while a via stranded between thin traces carries less. Parallel vias also lower resistance and inductance, which is why a via array beats one oversized hole.

Worked examples

Real sizing calls, and the number that decides each one.

Scenario	Result	Why
Two 0.3 mm vias, 25 um plating, 10 C rise, through-hole	≈ 3.8 A	Each via carries about 1.9 A; the pair sums, before any margin.
Need 8 A across 0.3 mm / 25 um through-hole vias at 10 C	5 vias (19% margin)	1.9 A each, so five gives 9.5 A - the smallest count that clears 8 A.
3 A forced through a single 0.3 mm via	≈ 28 C rise	Well past a 10 C target - one small via is the hot spot; split the current across several.
Same via, but blind/buried	≈ 1.0 A	The inner-layer constant (0.024) roughly halves the rating versus through-hole.

How this relates to other standards

Standard / tool	Relationship	What it means
IPC-2221C §6.2	Method from	The conductor current-vs-area-vs-temperature relation, applied here to the via barrel instead of a trace.
IPC-2152	Refined by	The modern, test-based current-capacity standard; it can permit more current than IPC-2221 but needs fuller thermal inputs.
PCB trace width	Same standard as	The trace either side of the via is sized by the same IPC-2221 method - size them together so the via is not the bottleneck.

A conservative, steady-state DC estimate for first-pass sizing and fabrication discussion - not final sign-off on a critical power path. It does not model skin effect, current crowding, via inductance, or the extra cooling from connected planes. Vias dump heat into copper, so real capacity is often higher; confirm the guaranteed minimum plating and finished hole with your fabricator.

Where engineers use this

Layer-to-layer power delivery

Stitching a power rail from a top-side connector down to inner planes, where one via is rarely enough and an array shares the current.

Point-of-load regulators

Sizing the via array on a buck converter output so the barrels carry the rail current without becoming the hot spot.

Thermal vias under power parts

Estimating how an array of plated vias both carries current and conducts heat into an inner plane below a hot component.

Frequently asked questions

Does the hole diameter or the plating set the current?

Both, through the barrel cross-section. A bigger hole gives more circumference and thicker plating gives more wall, and the product (about pi x drill x plating) is the copper area that carries current. The empty hole carries nothing, which is why a large unplated-looking via can still be limited by thin plating.

Should I use the inner or outer IPC-2221 constant for a via?

This tool uses the outer constant (0.048) for through-hole vias and the inner constant (0.024) for blind/buried, following common practice. Through-hole vias touch the outer layers and get some convection; blind/buried vias are sealed inside. For critical power paths many designers conservatively use the inner value for all vias - take the lower number if unsure.

How many vias do I need for a power rail?

Use the Vias needed mode: enter the target current and via geometry and it returns the smallest count that meets it, with the resulting margin. As a habit, round up for symmetry and keep headroom - vias cool poorly and real arrays see manufacturing spread in plating and hole size.

Is IPC-2221 accurate for vias?

It is a conservative first-pass estimate. Real vias usually carry more because they dump heat into connected planes and copper, which the bare formula ignores; IPC-2152 models that better but needs more inputs. Treat this as sizing and fabrication-discussion input, not final sign-off on a critical power path.

Does this cover high-frequency or current crowding?

No. The model is steady-state DC. It does not include skin effect, current crowding at the via transition, or via inductance, all of which matter at high frequency or fast edges. For signal integrity, use an impedance and return-path analysis instead.

Does via-in-pad or filled/capped via change the rating?

Usually for the better. Epoxy-filled and capped vias, and via-in-pad designs, improve heat spreading and current capacity, so this calculator is a conservative baseline for them. Confirm the construction and the guaranteed minimum plating with your fabricator.

Guides

IPC-2221 vs IPC-2152Why the two standards disagree, and which to trust.

Sources: IPC-2221C, Generic Standard on Printed Board Design (§6.2, conductor current capacity) · IPC-2152, Standard for Determining Current-Carrying Capacity in Printed Board Design · L. Rozenblat, IPC-2152 universal curve-fit (still-air Fig 5-2), used as a via cross-check. Verify against the current edition.